Power conversion device with staggered power semiconductor modules

ABSTRACT

A power conversion device includes: a plurality of first power semiconductor modules in each of which a series circuit of a first semiconductor device and a second semiconductor device is built in, each of the plurality of first power semiconductor modules being connected in parallel with a series circuit of a first capacitor and a second capacitor connected in series with a DC power source; and a plurality of second power semiconductor module in each of which a bidirectional semiconductor device is built in, the bidirectional semiconductor device being connected between a connection point between the first capacitor and the second capacitor and one of connection points between the first semiconductor devices and the second semiconductor devices. Each of the first power semiconductor modules and the second power semiconductor modules are arranged on a mounting surface of a cooling body in a staggered arrangement.

CROSS REFERENCE TO RELATED APPLICATIONS AND INCORPORATION BY REFERENCE

This application claims benefit of priority under 35 USC 119 based onJapanese Patent Application No. 2016-228092 filed on Nov. 24, 2016, theentire contents of which are incorporated by reference herein.

TECHNICAL FIELD

The present invention relates to a power conversion device that isconstituted by connecting a plurality of power semiconductor modulesthat have different internal element configurations.

BACKGROUND ART

As a power conversion device of this type, for example, a three-levelpower conversion device that is constituted by constituting a powerconversion circuit for one phase and including such power conversioncircuits for three phases has been proposed (see, for example, JP2014-36509 A). In the above, the power conversion circuit for one phaseis constituted with a 2-in-1 module that is constituted by connecting,in series, a first IGBT to which a flyback diode is connected in inverseparallel and a second IGBT to which a flyback diode is likewiseconnected in inverse parallel and containing the connected IGBTs in onepackage and a bidirectional switch module that contains, in a package, abidirectional switch, which has a characteristic of allowing a currentto flow in both directions.

In the conventional art described in JP 2014-36509 A, on a cooling fin,a first region in which three 2-in-1 modules are arranged in paralleland a second region in which three bidirectional switch modules arearranged in parallel are formed. The respective 2-in-1 modules andbidirectional switch modules and capacitors are electricallyinterconnected by a laminated bus bar.

SUMMARY OF INVENTION

In the conventional art described in JP 2014-36509 A, on the coolingfin, a region for arranging the 2-in-1 modules, in each of which a firstIGBT and a second IGBT are built in, in parallel and a region forarranging the bidirectional switch modules, in each of which abidirectional switch element is built in, in parallel are formed in adivided manner. In the above, in a 2-in-1 module, a first IGBT andsecond IGBT in which element loss increases when a device power factoris close to 1 are built in, and, in a bidirectional switch module, abidirectional switch element in which element loss increases when thedevice power factor is close to 0 is built in.

Therefore, there is a problem in that, since, in both cases of a highdevice power factor and a low device power factor, elements the loss ofwhich becomes high are arranged in a concentrated manner to either thedivided first region or second region on the cooling fin, the coolingfin cannot exert sufficient cooling capability.

It has been well known that, in a power conversion device, a surgevoltage is generated across a switch element in accordance with acurrent change rate and a wiring parasitic inductance in performingswitching.

When a switching operation is speeded up in order to reduce elementloss, a problem is caused in that a surge voltage in performing theswitching operation increases in proportion to an increase in the timerate of change in a main circuit current and a required withstandvoltage of a switching element increases.

Although reducing the wiring parasitic inductance by increasing thepackaging density of 2-in-1 modules and bidirectional switch modules ona cooling fin is applicable, another problem is caused in that heatgeneration density increases.

Accordingly, the present invention is made by taking notice of suchproblems in the above-described conventional art, and an object of thepresent invention is to provide a power conversion device that iscapable of not only increasing cooling efficiency but also reducingwiring parasitic inductance in connecting a plurality of modules thathave different internal element configurations in parallel.

In order to achieve the object mentioned above, according to an aspectof the present invention, there is provided a power conversion deviceincluding: a plurality of first power semiconductor modules in each ofwhich a series circuit of a first semiconductor device and a secondsemiconductor device is built in, each of the plurality of first powersemiconductor modules being connected in parallel with a series circuitof a first capacitor and a second capacitor connected in series with aDC power source; and a plurality of second power semiconductor module ineach of which a bidirectional semiconductor device is built in, thebidirectional semiconductor device being connected between a connectionpoint between the first capacitor and the second capacitor and one ofconnection points between the first semiconductor devices and the secondsemiconductor devices. Each of the first power semiconductor modules andthe second power semiconductor modules are arranged on a mountingsurface of a cooling body in a staggered arrangement.

According to one aspect of the present invention, since 2-in-1 typefirst power semiconductor modules and second power semiconductor modulesin each of which a bidirectional switch element is built in are arrangedin a staggered arrangement on a mounting surface of a cooling body, heatgeneration regions on the mounting surface of the cooling body may bedispersed, and thus cooling efficiency of the first power semiconductormodules and the second power semiconductor modules by the cooling bodymay be improved. In addition, since a first power semiconductor moduleand a second power semiconductor module that are arranged in parallelwith each other can be electrically interconnected, wiring parasiticinductance may be reduced.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims. It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory and are not restrictive of the invention.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a plan view illustrative of a first embodiment of a powerconversion device according to the present invention;

FIG. 2 is an enlarged plan view illustrative of a U-phase output arm;

FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 2;

FIG. 4 is a side view of FIG. 2;

FIGS. 5A and 5B are perspective views illustrative of a laminated busbar, and FIG. 5A is a perspective view illustrative of an overallstructure of the laminated bus bar, FIG. 5B is an exploded perspectiveview of the laminated bus bar;

FIG. 6 is a circuit diagram illustrative of an equivalent circuit ofFIG. 1;

FIG. 7 is a circuit diagram illustrative of an equivalent circuit of aU-phase output arm in FIG. 6;

FIG. 8 is a signal waveform chart illustrative of an output currentwaveform from the U-phase output arm;

FIG. 9 is a diagram illustrative of current paths in an output arm;

FIG. 10 is a plan view illustrative of a variation of a three-levelthree-phase power conversion device according to the present invention;

FIG. 11 is a plan view illustrative of a three-level single-phase powerconversion device according to the present invention;

FIG. 12 is a circuit diagram illustrative of an equivalent circuit ofFIG. 11;

FIG. 13 is a plan view illustrative of a portion corresponding to onephase of a second embodiment of the power conversion device according tothe present invention;

FIG. 14 is a circuit diagram illustrative of a C snubber circuit that isapplicable to the second embodiment;

FIG. 15 is a circuit diagram illustrative of an RCD snubber circuit thatis applicable to the second embodiment;

FIG. 16 is a plan view when a snubber circuit built in chip is appliedto a conventional art; and

FIG. 17 is a circuit diagram illustrative of a variation of a secondpower semiconductor module.

DETAILED DESCRIPTION

Embodiments of the present invention will now be described withreference to the drawings. In the following description of the drawings,the same or similar reference signs are assigned to the same or similarportions. However, it should be noted that the drawings are schematicand relations between thicknesses and planar dimensions, ratios amongthicknesses of respective layers, and the like are different from actualones. Therefore, specific thicknesses and dimensions should bedetermined in consideration of the following description. It should alsobe noted that the drawings include portions having different dimensionalrelationships and ratios from each other.

In addition, the following embodiment indicates devices and methods toembody the technical idea of the present invention by way of example,and the technical idea of the present invention does not limit thematerials, shapes, structures, arrangements, and the like of theconstituent components to those described below. The technical idea ofthe present invention can be subjected to a variety of alterationswithin the technical scope prescribed by the claims described in CLAIMS.

First, an embodiment of a power conversion device that represents oneaspect of the present invention will be described.

First, a first power semiconductor module PM1 and a second powersemiconductor module PM2 to which the present invention is applicablewill be described.

As illustrated in FIG. 6, a first power semiconductor module PM1 isconstituted with a 2-in-1 module that is constituted by connecting, inseries, a first semiconductor device SD1 that constitutes an upper armA_(U) and a second semiconductor device SD2 that constitutes a lower armA_(L). In the above, the first semiconductor device SD1 is constitutedwith a semiconductor switching element Q1 that is made of an insulatedgate bipolar transistor (IGBT), a power MOSFET, and the like and aflyback diode D1 that is connected in inverse parallel with theswitching element Q1.

In a similar manner, a second semiconductor device SD2 is alsoconstituted with a switching element Q2 that is made of an insulatedgate bipolar transistor (IGBT), a power MOSFET, and the like and aflyback diode D2 that is connected in inverse parallel with theswitching element Q2.

As illustrated in FIGS. 1 to 3, the first power semiconductor module PM1is formed into an in-mold molded article in which the afore-describedfirst semiconductor device SD1 and second semiconductor device SD2 and awiring board (not illustrated) that connects them electrically arecovered with molding resin.

On the front surface of the first power semiconductor module PM1, a pairof pin-shaped positive electrode terminals Tp that are connected to apositive electrode of a DC power source, a pair of negative electrodeterminals Tn that are connected to a negative electrode of the DC powersource, and a pair of AC output terminals Tac that are connected to aload are arranged in this order from one end side toward the other endside with an identical inter-terminal distance kept therebetween.

Furthermore, a gate terminal Tg through which gate signals are suppliedto the first semiconductor device SD1 and the second semiconductordevice SD2, respectively, is formed on the opposite side of the positiveelectrode terminals Tp to the negative electrode terminals Tn. In theabove, each of the pair of positive electrode terminals Tp, the pair ofnegative electrode terminals Tn, and the pair of AC output terminals Tacis made up of two pin-shaped terminals that are formed projectingly witha prescribed distance kept therebetween in the width direction.

As illustrated in FIG. 6, the second power semiconductor module PM2 isconstituted with a bidirectional semiconductor device SD3 in which tworeverse blocking IGBTs Q3 and Q4 are connected in inverse parallel witheach other. As illustrated in FIGS. 1 to 3, the second powersemiconductor module PM2 is formed into an in-mold molded article inwhich the reverse blocking IGBTs Q3 and Q4 and a wiring board thatconnects them electrically are covered with molding resin.

On the front surface of the second power semiconductor module PM2, amiddle terminal Tm is formed projectingly on one end side, the AC outputterminal Tac is formed projectingly on the other end side, and the gateterminal Tg that supplies gate signals to the reverse blocking IGBTs Q3and Q4, respectively, is formed projectingly on the opposite side of themiddle terminal Tm to the AC output terminal Tac. In the above, each ofthe middle terminal Tm and the AC output terminal Tac is made up of apin-shaped terminal that is formed projectingly in the center in thewidth direction.

The first power semiconductor module PM1 and the second powersemiconductor module PM2 are formed in the same size, and the middleterminal Tm and the output terminal Tac of the second powersemiconductor module PM2 are formed at positions corresponding to thepositive electrode terminals Tp and the output terminals Tac of thefirst power semiconductor module PM1, respectively.

On the back surfaces of the first power semiconductor module PM1 and thesecond power semiconductor module PM2, heatsinks that dissipategenerated heat from internal semiconductor devices to the outside arepreferably arranged.

Next, a three-level three-phase power conversion device that isconstituted using first power semiconductor modules PM1 and second powersemiconductor modules PM2 will be described.

As illustrated in FIG. 6, a three-level three-phase power conversiondevice 10 described above includes a series circuit made up of a firstcapacitor C1 and a second capacitor C2, a U-phase output arm UA, aV-phase output arm VA, and a W-phase output arm WA that are connected inparallel between a positive electrode line Lp that is connected to thepositive electrode of a DC power source 11 and a negative electrode lineLn that is connected to the negative electrode of the DC power source11.

As illustrated in FIG. 6, a basic configuration of each of the U-phaseoutput arm UA, the V-phase output arm VA, and the W-phase output arm WAincludes a pair of a first power semiconductor module PM1 and a secondpower semiconductor module PM2.

That is, the first power semiconductor module PM1 has a firstsemiconductor device SD1 and a second semiconductor device SD2 connectedbetween the positive electrode line Lp and the negative electrode lineLn. The second power semiconductor module PM2 has a bidirectionalsemiconductor device SD3 connected between a connection point betweenthe first semiconductor device SD1 and the second semiconductor deviceSD2 and a connection point between the first capacitor C1 and the secondcapacitor C2.

In addition, as illustrated in FIG. 7, each of the U-phase output armUA, the V-phase output arm VA, and the W-phase output arm WA has aconfiguration in which a plurality of, for example, three, pairs of afirst power semiconductor module PM1 and a second power semiconductormodule PM2 are connected in parallel in order to acquire a required loadcurrent when a pair of a first power semiconductor module PM1 and asecond power semiconductor module PM2 is incapable of supplying asufficient load current required for a load.

When, as described above, each of the U-phase output arm UA, the V-phaseoutput arm VA, and the W-phase output arm WA is constituted using aplurality of pairs of a first power semiconductor module PM1 and asecond power semiconductor module PM2, three sets of first powersemiconductor modules PM11 to PM13 and second power semiconductormodules PM21 to PM23 are arranged on cooling bodies 21 that areconstituted with cooling fins or cooling pins, as illustrated in FIG. 1.

In the above, each cooling body 21 is formed of a metal member, such asaluminum and copper, having a high thermal conductivity. The coolingbody 21 is constituted with a module mounting plate section 21 a and alot of heat dissipation fins 21 c that are formed in a downwardprojecting manner on the opposite side of the module mounting platesection 21 a to a module mounting surface 21 b thereof.

As illustrated in FIG. 3, on the module mounting surface 21 b of eachmodule mounting plate section 21 a, three recessed sections 21 d, eachof which has a shallow depth and is to position a power semiconductormodule out of the three sets of the first power semiconductor modulesPM11 to PM13 and the second power semiconductor modules PM21 to PM23, inthe right and left directions in each of two rows, front and rear, thatis, six recessed sections 21 d in total, are formed.

As illustrated in FIG. 2 in an enlarged manner, in the U-phase outputarm UA, the first power semiconductor module PM11, the second powersemiconductor module PM21, and the first power semiconductor module PM12are arranged in parallel with one another in this order from the leftinto recessed sections 21 d in the front row in such a way that sidesurfaces of each pair of adjacent modules face each other with aprescribed distance kept therebetween to constitute a first module rowMr1.

In addition, into recessed sections 21 d in the rear row, the secondpower semiconductor module PM22, the first power semiconductor modulePM13, and the second power semiconductor module PM23 are arranged inparallel with one another in this order from the left in such a way thatside surfaces of each pair of adjacent modules face each other with aprescribed distance kept therebetween to constitute a second module rowMr2.

In the above, the first power semiconductor modules PM11 and PM12 in thefirst module row Mr1 are arranged in such a way that the gate terminalsTg thereof and the AC output terminals Tac thereof are positioned on thefront end side and on the rear end side, respectively. In addition, thesecond power semiconductor module PM21 in the first module row Mr1 isarranged in such a way that the gate terminal thereof and the AC outputterminal Tac thereof are positioned on the front end side and on therear end side, respectively.

The first power semiconductor module PM13 in the second module row Mr2is arranged in such a way that the gate terminals Tg thereof and the ACoutput terminals Tac thereof are positioned on the rear end side and onthe front end side, respectively. In addition, the second powersemiconductor modules PM22 and PM23 in the second module row Mr2 arearranged in such a way that the gate terminals Tg thereof and the ACoutput terminal Tac thereof are positioned on the rear end side and onthe front end side, respectively.

Therefore, on the module mounting plate section 21 a of the cooling body21, the first power semiconductor modules PM11 to PM13 and the secondpower semiconductor modules PM21 to PM23 are arranged in an alternatemanner in the planar view, that is, in a staggered arrangement, so thatthe first power semiconductor modules PM11 to PM13 and the second powersemiconductor modules PM21 to PM23 face each other in the front and reardirections.

The V-phase output arm VA and the W-phase output arm WA also includefirst module rows Mr1 and second module rows Mr2 that have the samearrangements as those of the U-phase output arm UA, and the first powersemiconductor modules PM11 to PM13 and the second power semiconductormodules PM21 to PM23 are arranged in an alternate manner in the planarview, that is in a staggered arrangement, so that the first powersemiconductor modules PM11 to PM13 and the second power semiconductormodules PM21 to PM23 face each other in the front and rear directions.

As illustrated in FIG. 4, in the U-phase output arm UA, the V-phaseoutput arm VA, and the W-phase output arm WA, the respective terminalsTp, Tn, and Tac of the first power semiconductor modules PM11 to PM13are electrically connected to a positive electrode bus bar Bp, anegative electrode bus bar Bn, and AC output bus bars Bac, respectively,and the respective terminals Tm and Tac of the second powersemiconductor modules PM21 to PM23 are electrically connected to amiddle bus bar Bm and the AC output bus bars Bac, respectively.

In the above, as illustrated in FIGS. 5A and 5B, each of the positiveelectrode bus bar Bp, the negative electrode bus bar Bn, and the middlebus bar Bm is constituted with a module connecting flat plate section 25having such a size as to cover the cooling bodies 21 of the U-phaseoutput arm UA, the V-phase output arm VA, and the W-phase output arm WAand a capacitor connecting bent section 26 bent upward from a rear endsection of the module connecting flat plate section 25 to form anL-shape in cross section.

In addition, as illustrated in FIG. 5A, a laminated bus bar LB isconstituted by laminating the negative electrode bus bar Bn, the middlebus bar Bm, and the positive electrode bus bar Bp in this order on theU-phase output arm UA, the V-phase output arm VA, and the W-phase outputarm WA with an insulating layer, such as an insulating film, interposedbetween each pair of successive bus bars.

The AC output bus bar Bac is arranged independently for each of threephases, that is, for each of the U-phase output arm UA, the V-phaseoutput arm VA, and the W-phase output arm WA. Each of the AC output busbars Bac is set to have such a size as to, in the planar view, cover theAC output terminals Tac of the first power semiconductor modules PM11 toPM13 and the second power semiconductor modules PM21 to PM23, which arearranged in a staggered arrangement. The AC output bus bars Bac arelaminated on the upper surface of the positive electrode bus bar Bp,which is the top layer, with insulating layers, such as an insulatingfilm, interposed therebetween.

To the positive electrode bus bar Bp, the negative electrode bus bar Bn,and the middle bus bar Bm, through-holes are formed through which thepositive electrode terminals Tp, the negative electrode terminals Tn,the AC output terminals Tac, and the middle terminals Tm of the firstpower semiconductor modules PM11 to PM13 and the second powersemiconductor modules PM21 to PM23, which are arranged in a staggeredarrangement, are inserted.

In the above, regarding the module connecting flat plate section 25 ofthe positive electrode bus bar Bp, through-holes that are formed atpositions corresponding to the positive electrode terminals Tp of thefirst power semiconductor modules PM11 to PM13 are set to have suchsizes as to allow the positive electrode terminals Tp to fit thereintoand to be electrically connected thereto, and through-holes that areformed at positions corresponding to other terminals are set to havesuch sizes as to allow the negative electrode terminals Tn, the ACoutput terminals Tac, and the middle terminals Tm to be insertedtherethrough without coming into contact therewith.

Regarding the module connecting flat plate section 25 of the negativeelectrode bus bar Bn, through-holes that are formed at positionscorresponding to the negative electrode terminals Tn of the first powersemiconductor modules PM11 to PM13 are set to have such sizes as toallow the negative electrode terminals Tn to fit thereinto and to beelectrically connected thereto, and through-holes that are formed atpositions corresponding to other terminals are set to have such sizes asto allow the positive electrode terminals Tp, the AC output terminalsTac, and the middle terminals Tm to be inserted therethrough withoutcoming into contact therewith.

Regarding the module connecting flat plate section 25 of the middle busbar Bm, through-holes that are formed at positions corresponding to themiddle terminals Tm of the second power semiconductor modules PM21 toPM23 are set to have such sizes as to allow the middle terminals Tm tofit thereinto and to be electrically connected thereto, andthrough-holes that are formed at positions corresponding to otherterminals are set to have such sizes as to allow the positive electrodeterminals Tp, the negative electrode terminals Tn, and the AC outputterminals Tac to be inserted therethrough without coming into contacttherewith.

Regarding the module connecting flat plate section 25 of the AC outputbus bar Bac, through-holes that are formed at positions corresponding tothe AC output terminals Tac of the first power semiconductor modulesPM11 to PM13 and the second power semiconductor modules PM21 to PM23 areset to have such sizes as to allow the respective AC output terminalsTac to fit thereinto and to be electrically connected thereto.

Furthermore, the capacitor connecting bent sections 26 of the positiveelectrode bus bar Bp, the middle bus bar Bm, and the negative electrodebus bar Bn are laminated in this order with an insulating layer, such asan insulating film, interposed between each pair of successive bus bars.The capacitor connecting bent sections 26 of the positive electrode busbar Bp, the middle bus bar Bm, and the negative electrode bus bar Bn areset to have such heights as to become higher in this order.

To the capacitor connecting bent section 26 of the positive electrodebus bar Bp, through-holes which positive electrode terminals tcp1 of aplurality of first capacitors C1, each of which is constituted with, forexample, an aluminum electrolytic capacitor, fit into and areelectrically connected to are formed.

To the capacitor connecting bent section 26 of the middle bus bar Bm,through-holes which the positive electrode terminals tcp1 of the firstcapacitors C1 are inserted through without coming into contact with andthrough-holes which negative electrode terminals tcn1 of the firstcapacitors C1 and positive electrode terminals tcp2 of a plurality ofsecond capacitors C2, each of which is similarly constituted with, forexample, an aluminum electrolytic capacitor, fit into and areelectrically connected to are formed.

To the capacitor connecting bent section 26 of the negative electrodebus bar Bn, through-holes which the positive electrode terminals tcp1and the negative electrode terminals tcn1 of the first capacitors C1 andthe positive electrode terminals tcp2 of the second capacitors C2 areinserted through without coming into contact with and through-holeswhich negative electrode terminals tcn2 of the second capacitors C2 fitinto and are electrically connected to are formed.

As described above, electrically interconnecting the positive electrodeterminals Tp, the negative electrode terminals Tn, and the AC outputterminals Tac of three sets of the first power semiconductor modulesPM11 to PM13 using the positive electrode bus bar Bp, the negativeelectrode bus bar Bn, and the AC output bus bar Bac, respectively, andelectrically interconnecting the middle terminals Tm and the AC outputterminals Tac of three sets of the second power semiconductor modulesPM21 to PM23 using the middle bus bar Bm and the AC output bus bars Bac,respectively, with respect to respective ones of the U-phase output armUA, the V-phase output arm VA, and the W-phase output arm WA enable theU-phase output arm UA, the V-phase output arm VA, and the W-phase outputarm WA illustrated in FIG. 7 to be formed individually.

In the U-phase output arm UA, the V-phase output arm VA, and the W-phaseoutput arm WA, with respect to each arm, the first power semiconductormodules PM11 to PM13 are simultaneously driven by gate signalsindividually given to the first semiconductor switching elements Q1 andthe second semiconductor switching elements Q2, and the second powersemiconductor modules PM21 to PM23 are also simultaneously driven bygate signals individually given to the third semiconductor switchingelements Q3 and the fourth semiconductor switching elements Q4.

For example, the U-phase output arm UA repeating four operation modesincluding a first operation mode, a second operation mode, a thirdoperation mode, and a fourth operation mode sequentially causes an ACcurrent to be output to a load.

In the first operation mode, starting from a state in which an outputcurrent is 0, the output current is increased to a positive mediumcurrent value by switching-controlling the third semiconductor switchingelements Q3 in the second power semiconductor modules PM21 to PM23 andnext increased to a maximum current value on the positive side andsubsequently decreased to the positive medium current value byswitching-controlling the first semiconductor switching elements Q1 inthe first power semiconductor modules PM11 to PM13.

In the second operation mode, the positive output current is decreasedfrom the positive medium current value to the vicinity of 0 byswitching-controlling the third semiconductor switching elements Q3 inthe second power semiconductor modules PM21 to PM23, and, when theswitching control of the third semiconductor switching elements Q3 isstopped, a flyback current flows to the load side through the flybackdiodes D2 of the second semiconductor switching elements Q2 in the firstpower semiconductor modules PM11 to PM13 and the output current returnsto 0.

In the third operation mode, the output current is increased to anegative medium current value by switching-controlling the fourthsemiconductor switching elements Q4 in the second power semiconductormodules PM21 to PM23, and next increased to a maximum current value onthe negative side and subsequently decreased to the negative mediumcurrent value by switching-controlling the second semiconductorswitching elements Q2 in the first power semiconductor modules PM11 toPM13.

In the fourth operation mode, the negative output current is decreasedfrom the negative medium current value to the vicinity of 0 byswitching-controlling the fourth semiconductor switching elements Q4 inthe second power semiconductor modules PM21 to PM23, and, when theswitching control of the fourth semiconductor switching elements Q4 isstopped, a flyback current flows to the power source side through theflyback diodes D1 of the first semiconductor switching elements Q1 inthe first power semiconductor modules PM11 to PM13 and the outputcurrent returns to 0.

As described above, performing the first to fourth operation modesrepeatedly enables a three-level AC output current to be formed, asillustrated in FIG. 8.

Performing the same control with phases delayed by 120° and 240° fromthe phase of the U-phase output arm UA for the V-phase output arm VA andthe W-phase output arm WA, respectively, enables a three-levelthree-phase output current to be output.

Therefore, according to the above-described first embodiment, the firstpower semiconductor modules PM11 to PM13 and the second powersemiconductor modules PM21 to PM23 are arranged in a staggered mannerinto the recessed sections 21 d formed on the module mounting surface 21b of the module mounting plate section 21 a of the cooling body 21.Accordingly, for example, the first power semiconductor module PM11 andthe second power semiconductor module PM21, which are adjacent to eachother, may constitute a U-phase arm set.

With the above-described configuration, a go-around loop in theswitching operation is made up of a path going through the firstcapacitor C1, the first semiconductor switching element Q1, the fourthsemiconductor switching element Q4, and the first capacitor C1 in thisorder and a path going through the second capacitor C2, the thirdsemiconductor switching element Q3, the second semiconductor switchingelement Q2, and the second capacitor C2 in this order in an upper armswitching operation and a lower arm switching operation, respectively,as illustrated in FIG. 9. The above-described configuration enableswiring inductance in both paths described above to be decreased, whichenables a surge voltage in the turn-off of the semiconductor switchingelements Q1 to Q4 and a surge voltage in the reverse recovery of theflyback diodes D1 and D2, which are connected to the semiconductorswitching elements Q1 and Q2 in inverse parallel, to be reduced.

In addition, arranging the first power semiconductor modules PM11 toPM13 and the second power semiconductor modules PM21 to PM23 in astaggered manner enables a wiring length between the first powersemiconductor module PM13, which serves as a main module, and the firstcapacitor C1 and second capacitor C2 to be shortest as in, for example,the U-phase output arm UA and the W-phase output arm WA, which, as aconsequence, enables wiring inductance to be reduced.

In this connection, when the first power semiconductor modules PM11 toPM13 and the second power semiconductor modules PM21 to PM23 arearranged in the same manner as the conventional art, the second powersemiconductor modules PM21 to PM23 are arranged between the firstcapacitors C1 and second capacitors C2 and the first power semiconductormodules PM11 to PM13, which causes a wiring length between the firstcapacitors C1 and second capacitors C2 and the first power semiconductormodules PM11 to PM13 to be lengthened by the length of the second powersemiconductor modules PM21 to PM23 to increase the wiring inductance.

In addition, when a device power factor is high, the first powersemiconductor modules PM11 to PM13, which are arranged in a staggeredmanner, generate more heat, and, when the device power factor is low,the second power semiconductor modules PM21 to PM23, which are alsoarranged in a staggered manner, generate more heat. Accordingly, it ispossible to keep a long distance between power semiconductor modulesthat simultaneously generate heat, and dispersing power semiconductormodules generating heat on the cooling body enables a rise intemperature at semiconductor devices that are built in in the powersemiconductor modules to be suppressed. Therefore, it is possible todecrease distances between first power semiconductor modules and secondpower semiconductor modules that are adjacent to each other and tominiaturize the cooling body 21 and, as a consequence, to carry outoptimum design.

Although, in the above-described first embodiment, a case in which thefirst power semiconductor modules PM11 to PM13 and the second powersemiconductor modules PM21 to PM23 are arranged in the same staggeredarrangement with respect to the U-phase output arm UA, the V-phaseoutput arm VA, and the W-phase output arm WA was described, thearrangement is not limited to the one in the case.

For example, exchanging the front and rear positions between the firstmodule row Mr1 and the second module row Mr2 in the V-phase output armVA enables, when the U-phase output arm UA, the V-phase output arm VA,and the W-phase output arm WA are aligned, all the first powersemiconductor modules PM11 to PM13 and the second power semiconductormodules PM21 to PM23 over the entirety of the output arms to be arrangedin a staggered arrangement, as illustrated in FIG. 10.

Although, in the above-described first embodiment, a case in which thepresent invention is applied to the three-level three-phase powerconversion device 10 was described, the present invention is not limitedto the case, and the present invention is also applicable to athree-level single-phase power conversion device.

A three-level single-phase power conversion device 30 described above isachieved by omitting an output arm dealing with any one phase (forexample, W-phase) in the afore-described three-level three-phase powerconversion device 10, setting, for example, the U-phase output arm UAand the V-phase output arm VA as a first output arm FA and a secondoutput arm SA, respectively, and connecting the two output arm sets inparallel to constitute an H-bridge circuit, as illustrated in FIGS. 11and 12.

Each of the first output arm FA and the second output arm SA isconstituted with a plurality of first power semiconductor modules PM11to PM13 and a plurality of second power semiconductor modules PM21 toPM23 in the same manner as in the afore-described first embodimentillustrated in FIG. 7.

As illustrated in FIG. 11, in the first output arm FA, on a cooling body21, the first power semiconductor module PM11, the second powersemiconductor module PM21, and the first power semiconductor module PM12are arranged in this order from the left in the front row and the secondpower semiconductor module PM22, the first power semiconductor modulePM13, and the second power semiconductor module PM23 are arranged inthis order from the left in the rear row.

In addition, the first power semiconductor modules PM11 to PM13 and thesecond power semiconductor modules PM21 to PM23 in the first output armFA and the second output arm SA are connected by a positive electrodebus bar Bp, a negative electrode bus bar Bn, a middle bus bar Bm, and ACoutput bus bars Bac.

Even the three-level single-phase power conversion device 30 providesthe same operational effects as those of the first embodiment exceptsupplying three-level single-phase AC output in place of three-levelthree-phase AC output by omitting a circuit dealing with any one phasein the afore-described first embodiment because the arrangement of thefirst power semiconductor modules PM11 to PM13 and the second powersemiconductor modules PM21 to PM23 constituting the first output arm FAand the second output arm SA is the same staggered arrangement as in thefirst embodiment.

Next, a second embodiment of the power conversion device according tothe present invention will be described using FIGS. 13 to 16.

The second embodiment is an embodiment in which snubber circuit built inchips in each of which a snubber circuit is built in are configured tobe connected in the afore-described first embodiment.

That is, in the second embodiment, a snubber circuit built in chip 31 inwhich a snubber circuit is built in is connected between each pair of afirst power semiconductor module PM1 and a second power semiconductormodule PM2 that are adjacent to each other in the arrangement directionwith respect to each of a U-phase output arm UA, a V-phase output armVA, and a W-phase output arm WA. In the second embodiment, descriptionwill be made using the V-phase output arm VA as an example.

The snubber circuit built in chip 31 is a four-terminal semiconductorchip and includes a first positive/negative electrode terminal tpn1, asecond positive/negative electrode terminal tpn2, a first middleterminal tm1, and a second middle terminal tm2, as illustrated in FIG.13. The first positive/negative electrode terminal tpn1 is electricallyconnected to one of positive electrode terminals Tp and negativeelectrode terminals Tn of a first power semiconductor module PM1. Thesecond positive/negative electrode terminal tpn2 is electricallyconnected to the other of the positive electrode terminals Tp and thenegative electrode terminals Tn of the first power semiconductor modulePM1. Either the first middle terminal tm1 or the second middle terminaltm2 is electrically connected to a middle terminal Tm of a second powersemiconductor module PM2.

Although, as a snubber circuit that is built in in the snubber circuitbuilt in chip 31, a C snubber circuit 32 illustrated in FIG. 14 and aRCD snubber circuit 33 illustrated in FIG. 15 are applicable, thesnubber circuit is not limited to a C snubber circuit and an RCD snubbercircuit and other various types of snubber circuits are applicable.

As illustrated in FIG. 14, the C snubber circuit 32 includes a firstsnubber capacitor Cs1 that is connected between the firstpositive/negative electrode terminal tpn1 and the first middle terminaltm1 and a second snubber capacitor Cs2 that is connected between thesecond positive/negative electrode terminal tpn2 and the second middleterminal tm2. In addition, the first middle terminal tm1 and the secondmiddle terminal tm2 of the C snubber circuit 32 are electricallyinterconnected directly.

As illustrated in FIG. 15, the RCD snubber circuit 33 includes a firstsnubber capacitor Cs1 and a first snubber resistor Rs1 that areconnected in series between the first positive/negative electrodeterminal tpn1 and the first middle terminal tm1 and a first snubberdiode Ds1 that is connected in parallel with the first snubber resistorRs1. The anode and cathode of the first snubber diode Ds1 are connectedto a connection point between the first positive/negative electrodeterminal tpn1 and the first snubber resistor Rs1 and a connection pointbetween the first snubber resistor Rs1 and the first snubber capacitorCs1, respectively.

The RCD snubber circuit 33 also includes a second snubber capacitor Cs2and a second snubber resistor Rs2 that are connected in series betweenthe second positive/negative electrode terminal tpn2 and the secondmiddle terminal tm2 and a second snubber diode Ds2 that is connected inparallel with the second snubber resistor Rs2. The anode and cathode ofthe second snubber diode Ds2 are connected to a connection point betweenthe second positive/negative electrode terminal tpn2 and the secondsnubber resistor Rs2 and a connection point between the second snubberresistor Rs2 and the second snubber capacitor Cs2, respectively.

Furthermore, the first middle terminal tm1 and the second middleterminal tm2 of the RCD snubber circuit 33 are electricallyinterconnected directly.

As illustrated in FIG. 13, four snubber circuit built in chip 31 areconnected among first power semiconductor modules PM11 to PM13 andsecond power semiconductor modules PM21 to PM23 constituting the V-phaseoutput arm VA by, for example, soldering.

That is, between the first power semiconductor module PM11 and thesecond power semiconductor module PM21, a snubber circuit built in chip31 is connected with its first positive/negative electrode terminaltpn1, second positive/negative electrode terminal tpn2, and secondmiddle terminal tm2 electrically connected to negative electrodeterminals Tn of the first power semiconductor module PM11, positiveelectrode terminals Tp of the first power semiconductor module PM11, anda middle terminal Tm of the second power semiconductor module PM21,respectively. The second middle terminal tm2 is put in a non-connectionstate.

In a similar manner, between the first power semiconductor module PM12and the second power semiconductor module PM21, a snubber circuit builtin chip 31 is connected with its first positive/negative electrodeterminal tpn1, second positive/negative electrode terminal tpn2, andfirst middle terminal tm1 electrically connected to positive electrodeterminals Tp of the first power semiconductor module PM12, negativeelectrode terminals Tn of the first power semiconductor module PM12, anda middle terminal Tm of the second power semiconductor module PM21,respectively. The second middle terminal tm2 is placed on the secondmiddle terminal tm2 of the adjacent snubber circuit built in chip 31with an insulating member interposed therebetween to be put in anon-connection state.

In addition, between the first power semiconductor module PM13 and thesecond power semiconductor module PM22, a snubber circuit built in chip31 is connected with its first positive/negative electrode terminaltpn1, second positive/negative electrode terminal tpn2, and secondmiddle terminal tm2 electrically connected to negative electrodeterminals Tn of the first power semiconductor module PM13, positiveelectrode terminals Tp of the first power semiconductor module PM13, anda middle terminal Tm of the second power semiconductor module PM22,respectively. The first middle terminal tm1 is put in a non-connectionstate.

Furthermore, between the first power semiconductor module PM13 and thesecond power semiconductor module PM23, a snubber circuit built in chip31 is connected with its first positive/negative electrode terminaltpn1, second positive/negative electrode terminal tpn2, and first middleterminal tm1 electrically connected to the positive electrode terminalsTp of the first power semiconductor module PM13, the negative electrodeterminals Tn of the first power semiconductor module PM13, and themiddle terminal Tm of the second power semiconductor module PM23,respectively. The second middle terminal tm2 is put in a non-connectionstate.

According to the second embodiment, as with the afore-described firstembodiment, the first power semiconductor modules PM11 to PM13 and thesecond power semiconductor modules PM21 to PM23 are arranged in astaggered arrangement on a cooling body 21. Thus, in a first module rowMr1, the first power semiconductor module PM11, the second powersemiconductor module PM21, and the first power semiconductor module PM12are aligned in order with side surfaces of each pair of adjacent modulesfacing each other. In a second module row Mr2, the second powersemiconductor module PM22, the first power semiconductor module PM13,and the second power semiconductor module PM23 are aligned in order withside surfaces of each pair of adjacent modules facing each other.

Each snubber circuit built in chip 31 is constituted into afour-terminal chip including a first positive/negative electrodeterminal tpn1, a second positive/negative electrode terminal tpn2, afirst middle terminal tm1, and a second middle terminal tm2.

Therefore, in addition to the advantageous effects of the firstembodiment, the second embodiment enables a mounting area on which thesnubber circuit built in chip 31 is mounted to be secured between afirst power semiconductor module PM1 and a second power semiconductormodule PM2 that are adjacent to each other. In addition, wiringdistances between a snubber circuit built in chip 31 and a first powersemiconductor module PM1 and second power semiconductor module PM2 maybe set at a shortest distance to reduce wiring inductance. For thisreason, the configuration of a three-level power conversion device maybe miniaturized and, in conjunction therewith, the efficiency thereofmay be increased.

In this connection, when the first power semiconductor modules PM1 andthe second power semiconductor modules PM2 are arranged in separation asin the conventional art, a snubber circuit built in chip with fourterminals is inapplicable in connecting a snubber circuit built in chip,and it is required to arrange two snubber circuit built in chips 41 withtwo terminals in parallel and to connect the snubber circuit built inchips 41 between a first power semiconductor module PM1 and a secondpower semiconductor module PM2 using bus bars 42 and 43, as illustratedin FIG. 16.

In other words, it is required to connect the snubber circuit built inchips 41 between positions having a longest distance, that is, an outerside position of a first power semiconductor module PM1 and an outerside position of a second power semiconductor module PM2, and betweenpositions having a second longest distance, that is, a middle positionof the first power semiconductor module PM1 and the outer side positionof the second power semiconductor module PM2, via the bus bars 42 and43, respectively. Thus, the size of a mounting area for the snubbercircuit built in chips 41 increases, which causes the miniaturization ofa three-level power conversion device to be difficult. In addition,there is a problem in that an increase in wiring parasitic inductancecauses surge voltage suppression by a snubber circuit to be difficult towork and reducing element loss by means of speeding up of a switchingoperation to be difficult, which causes increasing the efficiency of athree-level power conversion device to be difficult.

On the other hand, in the above-described second embodiment, it ispossible to arrange a snubber circuit built in chip between a firstpower semiconductor module PM1 and a second power semiconductor modulePM2 that are adjacent and arranged in parallel to each other, whichenables the above-described problem in the conventional art to besolved.

Although the first and second embodiments of the present invention havebeen described above, the present invention is not limited to theembodiments and can be subjected to a variety of alterations andimprovements.

For example, an arrangement between the first power semiconductormodules PM11 to PM13 and the second power semiconductor modules PM21 toPM23 in the U-phase output arm UA and W-phase output arm WA and theV-phase output arm VA may be changed into a reverse arrangement byexchanging the front and rear positions between the first module row Mr1and second module row Mr2.

To semiconductor switching elements Q1 to Q4 that are built in in afirst power semiconductor module PM1 and a second power semiconductormodule PM2, not only IGBTs but also MOSFETs are applicable and, inconjunction therewith, without being limited to a case in which theswitching elements Q1 to Q4 are constituted with Si, at least a portionof the semiconductor switching elements may be constituted with powersemiconductor devices that are made of wide band gap semiconductors,such as SiC, GaN, and the like.

Without being limited to a case of being constituted with reverseblocking semiconductor switching elements Q3 and Q4, a bidirectionalsemiconductor device SD3 that is built in in the second powersemiconductor module PM2 may be constituted with a series circuit of abidirectional semiconductor switching element Q3′ and a diode D3 and aseries circuit, which is connected in parallel with the above seriescircuit, of a bidirectional semiconductor switching element Q4′ and adiode D4, as illustrated in FIG. 17. In this case, the bidirectionalsemiconductor switching element Q3′ and the diode D4 are connected inparallel, and the bidirectional semiconductor switching element Q4′ andthe diode D3 are connected in parallel.

The number of pairs of a first power semiconductor module PM1 and asecond power semiconductor module PM2 constituting an output arm is notlimited to three and may be set at two or four or more.

The laminated bus bar LB needs not be formed over a plurality of phasesas in the above-described embodiments and may be constituted in adivided manner with respect to each phase. Without being limited to acase of being formed in a flat plate shape, the positive electrode busbar Bp, the middle bus bar Bm, and the negative electrode bus bar Bnconstituting the laminated bus bar LB may be formed in a lattice shapeor in a strip shape with respect to each phase.

The present invention is not limited to a three-level power conversiondevice, and may be applied to another multilevel, four or more levels,power conversion device having output arms each constituted with a firstpower semiconductor module PM1 and a second power semiconductor modulePM2 in combination.

All examples and conditional language provided herein are intended forthe pedagogical purposes of aiding the reader in understanding theinvention and the concepts contributed by the inventor to further theart, and are not to be construed as limitations to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although one or more embodiments of thepresent invention have been described in detail, it should be understoodthat the various changes, substitutions, and alterations could be madehereto without departing from the spirit and scope of the invention.

REFERENCE SIGNS LIST

10 Three-level three-phase power conversion device

UA U-phase output arm

VA V-phase output arm

WA W-phase output arm

PM1, PM11 to PM13 First power semiconductor module

PM2, PM21 to PM23 Second power semiconductor module

Tp Positive electrode terminal

Tn Negative electrode terminal

Tac Output terminal

Tm Middle terminal

21 Cooling body

Mr1 First module row

Mr2 Second module row

Bp Positive electrode bus bar

Bn Negative electrode bus bar

Bm Middle bus bar

Bac AC output bus bar

25 Module connecting flat plate section

26 Capacitor connecting bent section

C1 First capacitor

C2 Second capacitor

30 Three-level single-phase power conversion device

31 Snubber circuit built in chip

tpn1 First positive/negative electrode terminal

tpn2 Second positive/negative electrode terminal

tm1 First middle terminal

tm2 Second middle terminal

32 C snubber circuit

33 RCD snubber circuit

The invention claimed is:
 1. A power conversion device comprising: acapacitor series circuit of a first capacitor and a second capacitorconnected in series with a DC power source; a plurality of first powersemiconductor modules in each of which a series circuit of a firstsemiconductor device and a second semiconductor device is built in, eachof the plurality of first power semiconductor modules being connected inparallel with the capacitor series circuit; and a plurality of secondpower semiconductor modules in each of which a bidirectionalsemiconductor device is built in, the bidirectional semiconductor deviceof each of the plurality of second power semiconductor modules beingconnected between a connection point between the first capacitor and thesecond capacitor and a connection point between the first semiconductordevice of a respective first semiconductor module among the plurality ofthe first power semiconductor modules and the second semiconductordevice of the respective first power semiconductor module, wherein theplurality of first power semiconductor modules and the plurality ofsecond power semiconductor modules are arranged on a mounting surface ofa cooling body in a staggered arrangement in which the plurality offirst power semiconductor modules are interspersed with the plurality ofsecond power semiconductor modules.
 2. The power conversion deviceaccording to claim 1, wherein in each of the plurality of first powersemiconductor modules, a positive electrode terminal, a negativeelectrode terminal, and an external connection terminal are arranged inorder on an identical terminal arrangement surface, and in each of theplurality of second power semiconductor modules, an external connectionterminal that is connected to the external connection terminal of therespective first power semiconductor module and a middle connectionterminal that is connected to a connection point between the firstcapacitor and the second capacitor are arranged on an identical terminalarrangement surface.
 3. The power conversion device according to claim1, wherein the plurality of first power semiconductor modules and theplurality of second power semiconductor modules are arranged on themounting surface of the cooling body in a first module row and a secondmodule row, in the first module row, one or more of the plurality offirst power semiconductor modules and one or more of the plurality ofsecond power semiconductor modules are aligned alternately, each of oneor more of the plurality of first power semiconductor modules arrangedin the first module row is positioned across from a respective one ofthe plurality of second power semiconductor modules arranged in thesecond module row, and each of one or more of the plurality of secondpower semiconductor modules arranged in the first module row ispositioned across from a respective one of the plurality of first powersemiconductor modules arranged in the second module row.
 4. The powerconversion device according to claim 3, wherein in the first module row,the plurality of first power semiconductor modules and the pluralitysecond power semiconductor modules have external connection terminalsaligned on one end side, and in the second module row, the plurality offirst power semiconductor modules and the plurality of second powersemiconductor modules have external connection terminals aligned on oneend side and facing the external connection terminals in the firstmodule row.
 5. The power conversion device according to claim 3, furthercomprising: a positive electrode bus bar configured to connect thepositive electrode terminals in the first module row and the secondmodule row to one another; a negative electrode bus bar configured toconnect the negative electrode terminals in the first module row and thesecond module row to one another; a middle bus bar configured to connectthe middle connection terminals in the first module row and the secondmodule row to one another; and output bus bars configured to connectoutput terminals facing each other in the first module row and thesecond module row to each other individually.
 6. The power conversiondevice according to claim 5, wherein the positive electrode bus bar, thenegative electrode bus bar, and the middle bus bar are constituted witha laminated bus bar.
 7. The power conversion device according to claim3, comprising: a snubber circuit built in chip in which a snubbercircuit is built in, the snubber circuit being connected between apositive electrode terminal and a negative electrode terminal of one ofthe plurality of first power semiconductor modules and a middleconnection terminal of a second power semiconductor module, which is oneof the plurality of second power semiconductor modules and is adjacentto the one of the plurality of first power semiconductor modules whosenegative electrode terminal is connected to the snubber circuit.
 8. Thepower conversion device according to claim 1, comprising: a three-levelthree-phase inverter constituted by connecting three output arms, eachof the output arms including at least one of the plurality of firstpower semiconductor modules and at least one of the plurality of secondpower semiconductor modules.
 9. The power conversion device according toclaim 8, wherein each of the output arms is constituted by connecting athe plurality of first power semiconductor modules in parallel andconnecting the plurality of second power semiconductor modules inparallel.
 10. The power conversion device according to claim 1, whereinat least one device among the respective first semiconductor devices ofthe plurality of first power semiconductor modules, the respectivesecond semiconductor devices of the plurality of first powersemiconductor modules, and the respective bidirectional semiconductordevices of the plurality of second power semiconductor modules isconstituted including a wide band gap semiconductor element.
 11. Thepower conversion device according to claim 1, wherein, on the mountingsurface of the cooling body, one of the plurality of first powersemiconductor modules is interposed between two of the plurality ofsecond power semiconductor modules, and one of the plurality of secondpower semiconductor modules is interposed between two of the pluralityof first power semiconductor modules.
 12. The power conversion deviceaccording to claim 1, wherein the plurality of first power semiconductormodules comprises two first power semiconductor modules and theplurality of second power semiconductor modules comprises two secondpower semiconductor modules, and the two first power semiconductormodules are interspersed with the two second power semiconductor modulesby being in a 2×2 arrangement in which the two first power semiconductormodules occupy one set of diagonal positions in the 2×2 arrangement andthe two second power semiconductor modules occupy another set ofdiagonal positions in the 2×2 arrangement.